1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing metal-oxide-semiconductor (MOS) devices.
2. Description of the Prior Art
A conventional MOS transistor generally includes a semi-conductor substrate, such as silicon, a source region, a drain region, a channel positioned between the source region and the drain region, and a gate located above the channel. The gate structure is composed of a gate dielectric layer, a gate conductive layer positioned on the gate dielectric layer, and spacers positioned on the sidewalls of the gate conductive layer. Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of the carriers in the channel. Therefore, how to improve the carrier mobility in order to increase the speed performance of MOS transistors with available process tools has become a major topic in the semiconductor field.
The formation of, for example, SiGe source/drain regions, is commonly achieved by epitaxially growing a SiGe epitaxial layer adjacent to the spacers in the epitaxy recess within the semiconductor substrate after forming the spacer. In this type of MOS transistor, a biaxial tensile strain is induced in the epitaxial silicon layer due to the silicon germanium, which has a larger lattice constant than silicon, and, as a result, the band structure is modified, and the carrier mobility increases. This enhances the speed performance of the PMOS transistor. Similarly, SiC source/drain regions may be used to enhance the speed performances of the NMOS transistor.
In conventional strained silicon transistor processes, disposable spacers are usually formed on the substrate to define the position of epitaxy recesses. The disposable spacers are then removed after the epitaxial layer is formed. The above-mentioned process of removing the disposable spacers may damage the top of gate structure or the epitaxial layer, thereby deteriorating the electrical performances of the devices. Accordingly, how to improve the conventional strained silicon transistor process is an essential topic for the nowadays semiconductor industry.